Presentation
Deep Reinforcement Learning Paradigm for Analog Design Automation
DescriptionWe propose a tool capable of Automating Analog Design Sizing at scale in an industrial setting that meets sign-off quality. There have been several academic papers which talk about optimizing analog circuit but most of them operate under the academic umbrella which prohibits them from being viable solutions in the industrial setting where there are complex device models, PVT and Mismatch (MC) simulations, complex topologies with large number of design variable and specifications that have to be met with certain priority.
The proposed tool addresses all these challenges and is proven within our company to be a "Real" Analog Design Optimization tool.
We use Deep Reinforcement Learning and unique reward shaping algorithms to optimally tune device parameters to meet design specifications provided by the designers. The tool optimizes the design across all PVT (Process, Voltage, Temperature) corners and Mismatch (Monte Carlo) corners to produce a optimized circuit that is indistinguishable from a manually fine tuned circuit expect for the fact that, it does this much faster and arrives at the best possible solution (at least as good as the designer). It does this within a practical timeframe while being computationally economical.
At TI the solution is widely deployed and, 100+ analog circuits/blocks have been optimized with the proposed solution.
The proposed tool addresses all these challenges and is proven within our company to be a "Real" Analog Design Optimization tool.
We use Deep Reinforcement Learning and unique reward shaping algorithms to optimally tune device parameters to meet design specifications provided by the designers. The tool optimizes the design across all PVT (Process, Voltage, Temperature) corners and Mismatch (Monte Carlo) corners to produce a optimized circuit that is indistinguishable from a manually fine tuned circuit expect for the fact that, it does this much faster and arrives at the best possible solution (at least as good as the designer). It does this within a practical timeframe while being computationally economical.
At TI the solution is widely deployed and, 100+ analog circuits/blocks have been optimized with the proposed solution.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor