Presentation
Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai
DescriptionMemory design in deep sub-micron nanometer technologies is riddled with numerous challenges. Dealing with device variability is an extremely challenging task and is aggravated for ultra-low voltage regime. Memory cell associated with peripheral circuits such as read-assist using wordline underdrive (WLUD) directly impacts the cell current and hence the performance of the memory. Memory cell current is extremely sensitive to wordline voltage level. Peripheral circuits such as sense-amplifier, write-assist, replica tracking, and other adaptive circuits need to be designed carefully minimizing variability.
We have demonstrated the use of AI augmented circuit optimization using ASO.ai technology considering variability prone read-assist circuit. AI based circuit optimization has been used in the last 2-3 years extensively for analog circuits like bandgap, VCO etc. which are typically not constrained by area. Here, we are demonstrating that the same technology can be used for critical memory circuits.
The optimizer runs a highly reduced set of simulations to optimize the target measurement. WLUD circuit being PVT adaptive, optimization across PVT corners is needed. Manual optimization is difficult to achieve due to large number of independent variables. We could optimize the read-assist circuit using ASO.ai in quick turnaround time of ~2 weeks including iterations in layout design and back-annotations compared to ~5 weeks with manual approach. We could further reduce the variability by 30% compared to manual approach. This resulted in a performance gain of ~10%. ASO.ai technology not only optimizes for performance but also for area and dynamic/static power metrics
We will also discuss our ongoing work that is targeting bit-cell optimization, where SNM (Static Noise Margin) and WM (Write Margin) are optimized to meet required target sigma. Here we are trading-off between SNM and WM maintaining the same bit-cell area.
We have demonstrated the use of AI augmented circuit optimization using ASO.ai technology considering variability prone read-assist circuit. AI based circuit optimization has been used in the last 2-3 years extensively for analog circuits like bandgap, VCO etc. which are typically not constrained by area. Here, we are demonstrating that the same technology can be used for critical memory circuits.
The optimizer runs a highly reduced set of simulations to optimize the target measurement. WLUD circuit being PVT adaptive, optimization across PVT corners is needed. Manual optimization is difficult to achieve due to large number of independent variables. We could optimize the read-assist circuit using ASO.ai in quick turnaround time of ~2 weeks including iterations in layout design and back-annotations compared to ~5 weeks with manual approach. We could further reduce the variability by 30% compared to manual approach. This resulted in a performance gain of ~10%. ASO.ai technology not only optimizes for performance but also for area and dynamic/static power metrics
We will also discuss our ongoing work that is targeting bit-cell optimization, where SNM (Static Noise Margin) and WM (Write Margin) are optimized to meet required target sigma. Here we are trading-off between SNM and WM maintaining the same bit-cell area.
Event Type
Engineering Presentation
TimeMonday, July 272:00pm - 2:15pm PDT
LocationSeaside Ballroom B
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