Presentation
Automated Verification and Performance Analysis for Chiplets
SessionSystem & Software Design
DescriptionChiplets allow flexibility of design, enabling higher yields and faster turnaround times compared to monolithic SoCs. As part of creating the Cadence chiplet development solution, various areas for automation were identified to speed up the emulation and performance processes, thereby reducing the time required to bring chiplet designs to market.
Provision of emulation platforms early in the design cycle allow real hardware to be used by stakeholders such as system architects and software developers, allowing them to kick-off their activities significantly earlier, and reducing inter-team dependencies by creating a cohesive flow between all departments.
The verification flow uses outputs from design automation to generate the simulation & emulation platforms, the verification environment and tests. Tests are written using the Accellera Portable Test and Stimulus Standard (PSS) to allow C code to be generated for different target platforms, reducing duplication and saving effort and time.
The flow further generates the performance testing suite allowing metrics to be automatically retrieved between any defined source and end point using the Cadence System Performance Analyser. Availability of performance metrics early in the design cycle results in earlier design closure, reducing late architectural changes and increasing confidence in functionality and performance.
Provision of emulation platforms early in the design cycle allow real hardware to be used by stakeholders such as system architects and software developers, allowing them to kick-off their activities significantly earlier, and reducing inter-team dependencies by creating a cohesive flow between all departments.
The verification flow uses outputs from design automation to generate the simulation & emulation platforms, the verification environment and tests. Tests are written using the Accellera Portable Test and Stimulus Standard (PSS) to allow C code to be generated for different target platforms, reducing duplication and saving effort and time.
The flow further generates the performance testing suite allowing metrics to be automatically retrieved between any defined source and end point using the Cadence System Performance Analyser. Availability of performance metrics early in the design cycle results in earlier design closure, reducing late architectural changes and increasing confidence in functionality and performance.
Event Type
Engineering Presentation
TimeMonday, July 2710:45am - 11:00am PDT
LocationSeaside Ballroom B
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