Presentation
Automated System for FPGA-Based SoC Prototyping
DescriptionDesigning System-on-Chips (SoCs) requires a well-organized development process. Pre-silicon validation/verification plays a crucial role; it can be performed in various ways. Here, simulation and prototyping are addressed. This presentation focuses on digital devices. Therefore, FPGA-based prototyping fits perfectly. SoC development requires significant time for RTL coding and IP integration. The design evolves daily. Continuous simulations are launched, and prototyping must keep pace. Hence, constant realignment between the two environments is necessary. The FPGA scenario differs slightly from the simulation one: some blocks must be replaced (memories, PLLs and others) when switching from one domain to another. This replacement essentially involves managing and modifying lists of source code files (Verilog, SystemVerilog and VHDL) used for simulation and FPGA synthesis. Given the complexity of modern designs, manual handling could lead to human mistakes. This presentation describes a system, based on Python scripts, for the automatic transition from simulation to prototyping (and back).
Event Type
Engineering Presentation
TimeWednesday, July 292:15pm - 2:30pm PDT
LocationSeaside Ballroom A