Presentation
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs
DescriptionFor large-scale SerDes designs, dynamic power integrity sign-off is becoming increasingly challenging due to growing design scale and performance demands. Modern SerDes integrate analog blocks, digital blocks, sensitive clocks, decaps with complex Power Delivery Network (PDN) design. Such designs can reach tens of millions of transistors and multi-million-node as design nodes shrinking, making full-chip dynamic EMIR sign-off and Chip Power Model (CPM) generation difficult. In addition, data rates are scaling from 56G to 112G and 224G, leading to higher switching activity and larger transient current peaks. Accurate sign-off and CPM generation require smaller, picosecond-level time resolution and long transient windows of up to hundreds of nanoseconds, making sign-off runtime even longer.
In traditional power integrity analysis, existing EMIR tools have limited distributed scalability for full-chip, multi-domain SerDes designs. Realistic dynamic simulations often exhibit low parallel efficiency and inefficient utilization of computing resources, resulting in long runtime to days or even weeks. To reduce runtime and resource usage, designers have to downsize current vector capture window or simplify extracted networks, which impacts overall power integrity analysis accuracy. Moreover, past early analysis is typically limited to simple static analysis, while dynamic analysis and CPM generation can only be performed at the sign-off stage, making chip-package-system PDN co-optimization hard to process in early stage.
Here, we adopt a distributed and scalable dynamic power integrity flow from early analysis to sign-off. Early-stage dynamic power integrity analysis based on Build Quality Metric (BQM) provides early EMIR insight and enables early CPM generation for package- and system-level power integrity analysis, allowing issues to be addressed earlier and reducing sign-off iterations. Distributed and scalable dynamic EMIR sign-off flow enables efficient full-chip analysis under realistic workloads through multi-machine, multi-thread parallelism, without simplifying extracted networks or reducing analysis windows. With the unified dynamic power integrity flow from early analysis to sign-off, analysis efficiency is significantly improved while maintaining accuracy and increasing confidence in SerDes design robustness.
keywords：large-scale Serdes designs, distributed and scalable, dynamic power integrity, Chip Power Model
In traditional power integrity analysis, existing EMIR tools have limited distributed scalability for full-chip, multi-domain SerDes designs. Realistic dynamic simulations often exhibit low parallel efficiency and inefficient utilization of computing resources, resulting in long runtime to days or even weeks. To reduce runtime and resource usage, designers have to downsize current vector capture window or simplify extracted networks, which impacts overall power integrity analysis accuracy. Moreover, past early analysis is typically limited to simple static analysis, while dynamic analysis and CPM generation can only be performed at the sign-off stage, making chip-package-system PDN co-optimization hard to process in early stage.
Here, we adopt a distributed and scalable dynamic power integrity flow from early analysis to sign-off. Early-stage dynamic power integrity analysis based on Build Quality Metric (BQM) provides early EMIR insight and enables early CPM generation for package- and system-level power integrity analysis, allowing issues to be addressed earlier and reducing sign-off iterations. Distributed and scalable dynamic EMIR sign-off flow enables efficient full-chip analysis under realistic workloads through multi-machine, multi-thread parallelism, without simplifying extracted networks or reducing analysis windows. With the unified dynamic power integrity flow from early analysis to sign-off, analysis efficiency is significantly improved while maintaining accuracy and increasing confidence in SerDes design robustness.
keywords：large-scale Serdes designs, distributed and scalable, dynamic power integrity, Chip Power Model
Event Type
Engineering Presentation
TimeTuesday, July 2811:15am - 11:30am PDT
LocationSeaside Ballroom B
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