Presentation
Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
DescriptionWhile cryptographic modules are digitally verified for logical correctness, they remain susceptible to physical side-channel attacks (SCA). This paper proposes a verification flow to determine whether in-depth analog verification is required for digitally verified cores by identifying security vulnerabilities rooted in analog anomalies. By leveraging efficient variation-aware analysis flamework, we achieve fast exploration of Points of Interest (PoI) at the transistor level. It was proven that when we heuristically select analog quantities such as delay time and charge consumption among the digital paths of secret information within a crypto core, the outliers appeared in their statistical distributions and requested further analog investigation. The effectiveness was demonstrated among 17 S-boxes in AES-128 bit core, including a particular one embedded with a Hardware Trojan (HT). Our statistical logic successfully flagged one unintentionally anomalous S-box and also another intentionally HT-embedded one as the PoI candidates for detailed analog verification. Subsequent Correlation Power Analysis (CPA) confirmed that these flagged PoIs revealed secret keys significantly faster than standard S-boxes. The proposed flow achieves signoff accuracy 10-1000x faster than brute-force SPICE simulations. This approach empowers designers to systematically and efficiently introduce analog verification processes for digital security modules.
Event Type
Engineering Presentation
TimeWednesday, July 2911:30am - 11:45am PDT
LocationSeaside Ballroom B