Presentation
Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
SessionSystem & Software Design
DescriptionAccurate Die-Size estimation during the design specification stage is a pivotal factor in determining the cost, manufacturability, and market competitiveness of modern Automotive System-on-Chip (SoC) products. Traditional estimation approaches, which rely on linear models and heuristics, often fall short due to the increasing complexity and diversity of SoC architectures, especially as they integrate numerous IP blocks with varying requirements. This presentation introduces a machine learning (ML) framework, leveraging Random Forest algorithms, to address these challenges by learning from historical project data - including RTL structure, hard macro specifications, architectural parameters, and physical design metrics (PNR data). The proposed workflow encompasses data collection, feature engineering, model training, and prediction phases, enabling module-level area estimation and aggregation to the full SoC die-size. Empirical results, based on data from three completed SoC projects and over 1800 unique RTL modules, demonstrate the framework's robustness, achieving an R² accuracy of up to 0.95 and a mean absolute percentage error (MAPE) of 16%. This ML-based approach aims to empower chip architects and system design engineers to perform high-confidence, early die-size planning, facilitating design exploration, area recovery analysis, and informed decision-making for competitive product development.
Event Type
Engineering Presentation
TimeMonday, July 2711:42am - 12:00pm PDT
LocationSeaside Ballroom B