Presentation
Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio
DescriptionHigh-speed digital blocks integrated within traditional Place & Route flows pose verification and implementation challenges that analog-centric methodologies cannot fully address. As process technologies scale and timing margins shrink, these blocks exhibit strong sensitivity to parasitics, layout-dependent effects, and high-frequency interactions, demanding enhanced automation and predictability. While the Cadence Virtuoso studio provides unmatched control for custom transistor-level design and leverages Cadence Innovus for digital automation, it lacks capabilities for automated Structured Data Path (SDP) file and routing constraint creation from source.
This work introduces a unified implementation approach that bridges this gap by enabling SDP-based placement for custom standard cells with auto-generating SDP file from schematic or Verilog, and creating routing constraints such as matching and shielding based on net prefixes/suffixes from schematic/Verilog. The methodology improves design scalability, reduces manual effort, and strengthens flow automation for high-speed digital blocks. By combining Virtuoso studio custom design flexibility with Innovus-driven automation, the proposed solution delivers a robust, layout-aware implementation flow suited for next-generation high-performance SoC and PHY architectures.
This work introduces a unified implementation approach that bridges this gap by enabling SDP-based placement for custom standard cells with auto-generating SDP file from schematic or Verilog, and creating routing constraints such as matching and shielding based on net prefixes/suffixes from schematic/Verilog. The methodology improves design scalability, reduces manual effort, and strengthens flow automation for high-speed digital blocks. By combining Virtuoso studio custom design flexibility with Innovus-driven automation, the proposed solution delivers a robust, layout-aware implementation flow suited for next-generation high-performance SoC and PHY architectures.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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