Presentation
Progress-Based Timeout Debug for Scalable SoC Verification
DescriptionTimeout failures are among the most resource-intensive issues in System-on-Chip (SoC) verification, frequently manifesting as silent execution hangs with no explicit diagnostic signature. In large-scale regression environments, such failures can consume a significant fraction of total simulation resources and account for a disproportionate share of debug effort. Conventional mechanisms,
including global watchdogs, UVM heartbeats, and waveform-based analysis, typically provide only reactive termination without isolating the underlying root cause across RTL, testbench, or firmware layers.
This paper introduces a deterministic and protocol-aware framework for timeout root-cause isolation in UVM-based verification environments. The framework integrates distributed telemetry agents, localized watchdogs, and transaction-aging monitors across verification layers to enable real-time
correlation of causal dependencies. Timeout events are automatically classified into architectural, testbench, and system-level handshake categories using temporal and protocol-aware analysis.
Across more than 500 large-scale regression runs, the proposed framework reduced average timeout debug effort by 65–75%, lowered re-run frequency by approximately 40%, and improved overall schedule predictability. By transforming non-diagnostic global hangs into localized, actionable failure signatures, this approach enables structured timeout debug and proactive failure prevention in modern SoC verification flows.
including global watchdogs, UVM heartbeats, and waveform-based analysis, typically provide only reactive termination without isolating the underlying root cause across RTL, testbench, or firmware layers.
This paper introduces a deterministic and protocol-aware framework for timeout root-cause isolation in UVM-based verification environments. The framework integrates distributed telemetry agents, localized watchdogs, and transaction-aging monitors across verification layers to enable real-time
correlation of causal dependencies. Timeout events are automatically classified into architectural, testbench, and system-level handshake categories using temporal and protocol-aware analysis.
Across more than 500 large-scale regression runs, the proposed framework reduced average timeout debug effort by 65–75%, lowered re-run frequency by approximately 40%, and improved overall schedule predictability. By transforming non-diagnostic global hangs into localized, actionable failure signatures, this approach enables structured timeout debug and proactive failure prevention in modern SoC verification flows.
Event Type
Engineering Presentation
TimeMonday, July 2710:30am - 10:45am PDT
LocationSeaside Ballroom A
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