Presentation
Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
DescriptionLocal layout effects (LLEs) in advanced analog nodes cause variations in device threshold voltage (Vth) and mobility that depend heavily on the placement of neighboring structures and the stress in the FEOL stack. Conventional flows require LVS, PEX, and post‑simulation, making iterative compensation time‑consuming and impractical for early‑stage design. This work introduces an artificial neural network (ANN)‑based surrogate model that predicts ΔVth using only the relative distances between devices, independent of LVS status. By starting from the saturated Vth and applying the predicted ΔVth, device placement can be optimized to reduce dummy area and improve matching.
To train the models, 180 k samples per LLE item were generated, and input features were reduced through binning by device type, achieving a target relative error below 0.05 %. The solution was integrated with Calibre (LVS & xACT) and validated on a 2‑nm SF pilot run. In the test case of a StrongARM latch comparator, the ANN‑driven approach—compared with manual designs that relied solely on legacy process knowledge—maintained a Vth standard deviation of zero and eliminated 33 % of unnecessary dummy regions, all without invoking full post simulation.
To train the models, 180 k samples per LLE item were generated, and input features were reduced through binning by device type, achieving a target relative error below 0.05 %. The solution was integrated with Calibre (LVS & xACT) and validated on a 2‑nm SF pilot run. In the test case of a StrongARM latch comparator, the ANN‑driven approach—compared with manual designs that relied solely on legacy process knowledge—maintained a Vth standard deviation of zero and eliminated 33 % of unnecessary dummy regions, all without invoking full post simulation.
Event Type
Engineering Presentation
TimeWednesday, July 291:30pm - 1:45pm PDT
LocationSeaside RM 7