Presentation
Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
DescriptionWith the advent of the A.I era, the amount of handling data of SOC has sky-rocketed and power consumption inevitably increased. To suppress this phenomenon, various low-power hardware architectures have been added to the SOC and consequently 1) "X" values that cause bugs at silicon level have appeared and 2) verification complexity and TAT have increased to detect "X". Emulator is a general solution for reducing verification time, but it degrades the quality of power verification since it can only express two logical states ("0" and "1"). In this study, we propose a high performance 4-state ("0", "1", "X", and "Z") RTL power-aware simulation methodology leveraging an emulator. This methodology focuses on the precise modeling of UPF (Unified Power Format) intents and 4-state logic, which are vital for capturing realistic power behavior. We demonstrate that the seamless verification of UPF-driven power scenarios at hardware speeds while maintaining the logic granularity of 4-state simulation. Finally, by applying to the latest SOC project, we confirm that there is a 35 times performance gain compared to conventional simulation.
Event Type
Engineering Presentation
TimeWednesday, July 291:30pm - 1:45pm PDT
LocationSeaside Ballroom A