Presentation
DFT Ready Design with SCO Canvas : Shift Left of DFT Designs
DescriptionAs semiconductor designs scale in complexity, Design-for-Test (DFT) has become a critical bottleneck, often delayed until the post-RTL freeze stages. This paper introduces a novel "DFT-Ready Design" methodology using SOC Canvas to bridge the chronic gap between system design and DFT. Unlike conventional flows where DFT engineers rely on fragmented pre-DFT information, our approach captures system-level functional intent—such as power, clock, and I/O configurations—via an intuitive GUI at the earliest architectural stages. SOC Canvas then automatically generates IEEE 1687-compliant hardware structures and integrated control logic, ensuring total data consistency across RTL, synthesis, and DFT. We validated this methodology in a large-scale AI accelerator project, successfully reducing the total design cycle by 25% while eliminating the manual iterations typically required for DFT logic insertion. By shifting DFT responsibilities to the left and automating the generation of test-control infrastructures, this work provides a scalable foundation for modern SoC and emerging chiplet ecosystems, ensuring that designs are inherently "DFT-ready" before synthesis begins.
Event Type
Engineering Presentation
TimeMonday, July 2711:45am - 12:00pm PDT
LocationSeaside Ballroom A
Similar Presentations