Presentation
Scalable, Emulation-Friendly,co-Simulation Testbench for Exhaustive RISC-V Cluster Configuration Verification
DescriptionModern RISC-V CPU clusters are delivered as highly parameterized design families, where variations in core count, microarchitecture, cache hierarchy, interconnect fabric, and system IP produce hundreds or thousands of legal RTL configurations. Verifying only a small number of representative configurations is insufficient, as functional and memory-model bugs may manifest only under specific parameter combinations. This paper presents a configuration-oriented, emulation-friendly co-simulation Testbench framework paired with a JSON-driven RTL generation flow that enables scalable verification across large RISC-V configuration spaces using a single reusable testbench. This Testbench flow integrates RISC-V architectural checking, a memory consistency model interface, and a C++ based verification methodology including instruction-accurate co-simulation with ISS and RVWMO memory-model validation, all while remaining design-agnostic with respect to core microarchitecture and cluster composition through a companion script, gen_rtl_top.py, which consumes JSON configuration descriptions to automatically synthesize consistent cluster top-level RTL for each configuration of cores, clusters, shared cache, and system IP. The same verification environment runs unmodified across Hardware simulation, hardware emulation,early Software bring up on emulation and open-source tools such as Verilator, enabling efficient, vendor-independent configuration-space exploration and high-throughput verification of complex RISC-V cluster families.
Event Type
Engineering Presentation
TimeWednesday, July 292:30pm - 2:45pm PDT
LocationSeaside Ballroom A