Presentation
Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
DescriptionAdvanced technology nodes with tighter BEOL metal widths and pitches have enabled area scaling with higher interconnect densities but have significantly increased Electromigration (EM) induced reliability risks from increased power densities and self-heating effects from Gate-all-around (GAA) architecture. Modern mobile SoC are designed to ambitious performance targets and within very tight design windows, making traditional foundry-rules based EM closure challenging.
In this presentation, we employ a Context and Thermally aware Statistical EM budgeting (SEB) flow as sign-off methodology that prioritizes realistic physical and thermal environments, accurate correlation of models to silicon data, and precise failure-rate (FR) estimation to deliver efficient and reliable EM closure for complex 2nm SoC design. Implementation of this risk-aware flow empowered designers to maximize performance while maintaining the FR within the allocated reliability budget. Consequently, this Design For Reliability (DfR) approach eliminated over two weeks of iterative manual re-design effort and saved computing resources, significantly improving the sign-off timeline.
The work can be summarized as:
1. Context-Thermal-Risk Aware Modeling: Predict accurate failure rates using SEB that incorporates physical environment and thermal coupling with accurate silicon-calibrated models.
2. Targeted Fixing: Enable performance optimization by shifting to risk-based EM closure, prioritizing fixes only for critical violations exceeding the reliability budget.
In this presentation, we employ a Context and Thermally aware Statistical EM budgeting (SEB) flow as sign-off methodology that prioritizes realistic physical and thermal environments, accurate correlation of models to silicon data, and precise failure-rate (FR) estimation to deliver efficient and reliable EM closure for complex 2nm SoC design. Implementation of this risk-aware flow empowered designers to maximize performance while maintaining the FR within the allocated reliability budget. Consequently, this Design For Reliability (DfR) approach eliminated over two weeks of iterative manual re-design effort and saved computing resources, significantly improving the sign-off timeline.
The work can be summarized as:
1. Context-Thermal-Risk Aware Modeling: Predict accurate failure rates using SEB that incorporates physical environment and thermal coupling with accurate silicon-calibrated models.
2. Targeted Fixing: Enable performance optimization by shifting to risk-based EM closure, prioritizing fixes only for critical violations exceeding the reliability budget.
Event Type
Engineering Presentation
TimeMonday, July 273:45pm - 4:00pm PDT
LocationSeaside Ballroom A