Presentation
In-Situ Architecture for Detecting and Mitigating Off-Chip Interface Attacks
DescriptionPhysical vulnerabilities in off-chip interfaces between sensors and secure microcontrollers expose systems to attacks such as data manipulation, spoofing, and hardware Trojans. Traditional countermeasures like shielding and tamper-evident enclosures are costly and impractical for low-cost designs. This work proposes an all-digital, in-situ architecture that leverages inherent system variability—arising from IC packaging, PCB traces, and process mismatches—to generate unique timing signatures for each sensor-controller pair during factory calibration. These signatures, derived from pulse width and skew measurements of data bus transitions, are stored in non-volatile memory and continuously monitored during in-field transactions. Deviations from expected signatures indicate tampering, triggering alerts or shutdowns. The solution is protocol-independent, incurs minimal area and power overhead, and integrates seamlessly into existing microcontroller interfaces. Results demonstrate reliable detection of interface anomalies without additional mechanical protection, offering a robust, low-cost alternative for securing sensor channels against physical attacks.
Event Type
Engineering Presentation
TimeWednesday, July 2910:30am - 10:45am PDT
LocationSeaside Ballroom B