Presentation
AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
DescriptionWhile 3D disaggregated chiplets are viewed as the future of chip design, the approach inherently has drawbacks in thermal performance. This is because some of the chiplets in a given 3D stack may not be in contact with a good heat sink. In traditional 2D design methodology, a good heat sink is usually assumed to exist, which allows thermal analysis to be deferred to the end of design cycle. In 3D disaggregate designs, however, we may not have the luxury of deferring thermal analysis, as thermal violations may not be fixable without contact to sufficient heat sink. Therefore, it is imperative to optimize for thermal behavior along with traditional performance, power, and area (PPA) metrics early in the design flow. In this work, we propose an AI-driven methodology to incorporate thermal-aware module placement that simultaneously optimizes for thermal and other PPA targets. This methodology automatically experiments with hundreds of thermal-constrained scenarios in heterogenous 3D chiplet stacks using AI-assisted analysis to achieve the best possible thermal and PPA results, while requiring minimal user guidance and intervention.
Event Type
Engineering Presentation
TimeMonday, July 2711:45am - 12:00pm PDT
LocationSeaside RM 7