Presentation
Hierarchical Functional Fault Grading with Auto-Identification of Observation Points for Faster Fault Coverage Closer in Complex SoCs
DescriptionAs System-on-Chip (SoC) designs transition toward massive scale and multi-die architectures, achieving near-zero Defective Parts Per Million (DPPM) is increasingly hampered by the limitations of traditional structural Design-for-Test (DFT). Scan-based testing frequently leaves critical coverage gaps in custom circuits, security blocks, and hard-to-detect logic—gaps that often manifest as expensive field returns. While functional verification patterns provide a solution to fill these voids, traditional "flat" SoC-level fault grading is currently rendered unfeasible by prohibitive runtimes that stretch into weeks and memory requirements that dwarf standard server capacities.
This paper introduces a paradigm shift in functional fault grading through a hierarchical, parallelized framework optimized for complex SoCs. Our methodology features two primary innovations:
Automated Identification of Optimal Observation Points: A smart algorithm that pinpoints the internal nodes with the highest impact on fault coverage, significantly reducing the manual effort required for coverage closure.
Hierarchical Partitioning for Parallel Simulation: A modular flow that breaks complex SoCs into sub-scopes, allowing fault grading to run in parallel and dramatically reducing the compute and memory footprint.
The effectiveness of this methodology is validated on a production-grade Tensor SoC. Our results demonstrate a transformative improvement in verification efficiency: a simulation of 10,000 faults—previously considered unfeasible due to convergence and runtime, was completed in hours using standard hardware. By converting weeks of simulation into a predictable two-day workflow, this scalable framework enables faster coverage closure and ensures superior silicon quality for the next generation of high-reliability SoC designs.
This paper introduces a paradigm shift in functional fault grading through a hierarchical, parallelized framework optimized for complex SoCs. Our methodology features two primary innovations:
Automated Identification of Optimal Observation Points: A smart algorithm that pinpoints the internal nodes with the highest impact on fault coverage, significantly reducing the manual effort required for coverage closure.
Hierarchical Partitioning for Parallel Simulation: A modular flow that breaks complex SoCs into sub-scopes, allowing fault grading to run in parallel and dramatically reducing the compute and memory footprint.
The effectiveness of this methodology is validated on a production-grade Tensor SoC. Our results demonstrate a transformative improvement in verification efficiency: a simulation of 10,000 faults—previously considered unfeasible due to convergence and runtime, was completed in hours using standard hardware. By converting weeks of simulation into a predictable two-day workflow, this scalable framework enables faster coverage closure and ensures superior silicon quality for the next generation of high-reliability SoC designs.
Event Type
Engineering Presentation
TimeTuesday, July 2811:45am - 12:00pm PDT
LocationSeaside RM 7