Presentation
Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
DescriptionAs hardware designs grow in complexity, Formal Verification (FV) often hits scalability walls, resulting in "bounded" proofs rather than full closure.Deep state-space exploration is limited by computational resources. Overcoming this typically requires "helper" assertions (invariants), but manually identifying and writing these is labor-intensive and requires deep micro-architectural knowledge. In this presentation, we present our findings where we used AI/ML & GenFV to generate helpers to achieve full proofs and reduce the verification cycle time
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor