Presentation
Automating DFT Intelligence: Addressing TCPF Hotspots at Source Through Design Aware Test Points in Systemrdl-to-RTL Generators
DescriptionAs SoC complexity scales, the resulting explosion in Automatic Test Pattern Generation (ATPG) pattern counts has become a primary driver of escalating manufacturing test costs. A critical bottleneck in this process is the emergence of "TCPF (Test cost Per Fault) Hotspots" across designs such as highly complex, auto-generated blocks such as Control and Status Registers (CSRs) that exhibit disproportionately high pattern counts due to deep combinational logic and structural bottlenecks like shared address buses. Traditional structural test point insertion often fails to address these architectural constraints effectively, as it operates on a late-stage netlist without design-specific context.
This paper proposes an "Extreme Left-Shift" methodology that moves DFT intelligence directly into the specification-to-RTL generation phase. By integrating Design-Aware Test Points (DATP) natively within a SystemRDL-to-RTL generator, we introduce architectural enhancements—including address parallelism, local protocol control, and optimized OR-reduction logic—that are structurally impossible to implement efficiently at the netlist level. This automated approach utilizes intelligent algorithms to analyze input RDL specifications and fine-tune DATP parameters at scale.
We demonstrate the efficacy of this methodology on a production-grade Tensor SoC. Experimental results show that while maintaining a minimal area overhead (~0.1%), the proposed DATP solution achieves a 4x improvement in TCPF at the IP level and a 50% overall reduction in ATPG pattern count at the top level compared to reference designs. By solving DFT bottlenecks at the source, this scalable framework provides a robust path for significantly reducing SoC test costs across the industry
This paper proposes an "Extreme Left-Shift" methodology that moves DFT intelligence directly into the specification-to-RTL generation phase. By integrating Design-Aware Test Points (DATP) natively within a SystemRDL-to-RTL generator, we introduce architectural enhancements—including address parallelism, local protocol control, and optimized OR-reduction logic—that are structurally impossible to implement efficiently at the netlist level. This automated approach utilizes intelligent algorithms to analyze input RDL specifications and fine-tune DATP parameters at scale.
We demonstrate the efficacy of this methodology on a production-grade Tensor SoC. Experimental results show that while maintaining a minimal area overhead (~0.1%), the proposed DATP solution achieves a 4x improvement in TCPF at the IP level and a 50% overall reduction in ATPG pattern count at the top level compared to reference designs. By solving DFT bottlenecks at the source, this scalable framework provides a robust path for significantly reducing SoC test costs across the industry
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor