Presentation
Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip
DescriptionIt has been observed for several years that transistors of different threshold voltage types (VT) in one chip may contain different silicon to SPICE gap (S2S). This gap may result in risk of yield loss when industry uses SS (all VTs at SS) and FF (all VTs at FF) in signoff because of omitting risk when one VT is fast but the other VT is slow. This risk on timing is called as VT skew. Currently, there is no efficient approach that can accurately quantize VT skew risk. To solve this issue, this study introduces an analytical metric and an Monte-Carlo (MC)-based solution to accurately model Vt skew impact. The analytical metric can help give early quick assessment and the MC-based solution has been developed inside EDA tool.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor