Presentation
Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
DescriptionAs semiconductor technology advances, the industry is moving from traditional monolithic SoC designs to heterogeneous integration enabled by advanced 2.5D and 3D IC packaging. These architectures deliver higher performance, improved power efficiency, and greater functionality by combining multiple dies in a single package. However, this shift introduces complex physical verification challenges that conventional single-die methodologies cannot address.
Traditional techniques like DRC and LVS, designed for monolithic SoCs, are inadequate for multi-die integration, which involves new elements such as vertical interconnects, micro-bumps, TSVs, and interposers with unique geometric and electrical constraints. Simple XOR-based checks fail to accurately validate bump alignment, and multi-die LVS is complicated by the lack of foundry-provided rule decks, requiring custom solutions and multiple iterations—leading to time-consuming, error-prone flows and schedule risks.
To overcome these challenges, a scalable 3D physical verification methodology is essential. Leveraging tools like Calibre 3DStack enables precise die-to-die connectivity checks, robust micro-bump and TSV alignment validation, and efficient hierarchical verification flows. This approach minimizes iterations, reduces risk, and supports next-generation heterogeneous integration by enabling hierarchy reuse for improved design efficiency and scalability.
Traditional techniques like DRC and LVS, designed for monolithic SoCs, are inadequate for multi-die integration, which involves new elements such as vertical interconnects, micro-bumps, TSVs, and interposers with unique geometric and electrical constraints. Simple XOR-based checks fail to accurately validate bump alignment, and multi-die LVS is complicated by the lack of foundry-provided rule decks, requiring custom solutions and multiple iterations—leading to time-consuming, error-prone flows and schedule risks.
To overcome these challenges, a scalable 3D physical verification methodology is essential. Leveraging tools like Calibre 3DStack enables precise die-to-die connectivity checks, robust micro-bump and TSV alignment validation, and efficient hierarchical verification flows. This approach minimizes iterations, reduces risk, and supports next-generation heterogeneous integration by enabling hierarchy reuse for improved design efficiency and scalability.
Event Type
Engineering Presentation
TimeMonday, July 2710:30am - 10:45am PDT
LocationSeaside RM 7