Presentation
Scalable, Protocol-Agnostic Clockless In-Band Reset Architecture for Serial Link IPs in Multi-Domain SoCs
DescriptionModern multi-domain SoCs almost always integrate serial link IPs, making reliable system reset a critical challenge, especially when clock generation circuitry is compromised. Conventional out-of-band reset schemes require dedicated pins, limiting scalability, while existing in-band reset solutions depend on clock availability, rendering them unreliable in certain failure scenarios. This paper introduces a scalable, protocol-agnostic, clockless in-band reset architecture that ensures deterministic SoC reset through precise reset pulse width generation without relying on any clock source. The proposed design partitions functionality into PHY and controller blocks, incorporating a Reset Pattern Detector (RPD) for robust reset signaling. Demonstrated on an MIPI I3C controller subsystem, the architecture is easily portable to PCIe, eSPI, USB, SATA, DisplayPort, Ethernet, and other protocols. Key advantages include guaranteed reset duration, independence from SoC size or complexity, technology agnosticism, and non-intrusiveness to existing IP standards. This approach significantly enhances system reliability and scalability for heterogeneous SoCs, supporting error recovery, synchronization, and security-critical applications across diverse wired interfaces.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor