Presentation
Intelligent Clock Domain Crossing: Activity-Aware Synchronization for Low-Power SoCs
DescriptionModern SoCs integrate multiple asynchronous clock domains, making Clock Domain Crossing (CDC) for control signals a critical design challenge. Conventional n-flop synchronizers, though robust, remain continuously clocked, causing significant dynamic power dissipation and area overhead—especially when control signals toggle sparsely. This paper introduces an activity-aware CDC architecture that intelligently gates synchronizer clocks, activating only during signal transitions. By grouping control signals into synchronizer banks and employing transition detection, the proposed method drastically reduces idle power while preserving CDC fidelity. As demonstrated in 28 nm FDSOI at 600 MHz, the architecture achieves up to 90% dynamic power savings for low toggle rates and over 30% area reduction compared to traditional synchronizer designs. Results highlight scalability for large SoCs with thousands of control signals, delivering exceptional energy efficiency without functional compromise. Fully digital and technology-agnostic, this solution enables automated integration into RTL flows, making it ideal for next-generation low-power, high-performance systems.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor