Presentation
A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
DescriptionPower consumption plays a key factor in SoC. With advances made in wireless technologies through 3GPP LTE & NR, IEEE Wifi and now with 3GPP 6G, there is a need for advanced architecture in SoC. Typically, a SoC uses sleep and wakeup (warmboot) procedure for saving battery. The warmboot procedure involves changing DRAM from refresh mode to active mode. This takes certain time until which other operations get delayed. Also usage of DRAM further consumes power. Hence, hardware design that enables software to have systematic control on wakeup (warmboot) and sleep operations is required. This idea discusses on design of SoC to use hybrid mode of SRAM and DRAM. SRAM and DRAM are memory entities which play a key role in wakeup, software execution and sleep. With combination of software control on proposed hardware design for system-on-chip, can efficiently increase sleep time by minimizing DRAM usage and wakeup time by managing with SRAM along with faster execution of procedures required during wakeup.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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