Presentation
Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies
DescriptionFormal verification rigorously explores all possible system states, offering unmatched coverage and the ability to detect subtle errors in complex designs. However, its exhaustive nature leads to the state space explosion problem, making verification computationally challenging. Reset abstraction mitigates this by simplifying the state space while preserving essential properties, but its application is often hindered by difficulties in selecting the right abstraction level and ensuring results of accuracy. Many engineers view reset abstraction as unpredictable and hard to control; a perception compounded by the scarcity of practical literature detailing effective strategies, common pitfalls, and best practices. To address these challenges, we introduced effective step-by-step Reset Abstraction methodology that has been validated by conducting case studies on multiple design blocks from our PCIe verification project. Our methodology delivers a comprehensive framework, beginning with precise identification of the optimal signals for abstraction and extending through rigorous analysis of potential pitfalls. By proactively anticipating and managing the risks, greater control and reliability over the method is enabled. This not only enhances the practical effectiveness of reset abstraction but also empowers engineers to apply it with increased confidence and efficiency, maximizing its potential in real-world verification environments.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor