Presentation
LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits
DescriptionPlacement quality strongly impacts routability and timing in DRAM peripheral circuits. While expert designers manually identify structural patterns of cells to be clustered during placement in small scale circuits to enhance the quality of results (QoR), this approach does not scale to large DRAM peripheral designs.
This research proposes an automated cell clustering method using large language models (LLMs) for DRAM peripheral circuit placement. Expert knowledge describing the target structural patterns for clustering is written as natural language prompts. These prompts enable the LLM to interpret the netlist as a graph and identify the target structural patterns. The identified clusters are treated as single placement instances to achieve structure-aware placement. The proposed approach allows flexible detection of target structures and remains robust to structural variations without explicit rule-based programming.
Experimental results on a DRAM peripheral circuit demonstrate a 80.6% reduction in the number of DRVs. Setup WNS improves by 0.9% while hold WNS degrades by 128%, highlighting the importance of timing-aware clustering as future work.
This research proposes an automated cell clustering method using large language models (LLMs) for DRAM peripheral circuit placement. Expert knowledge describing the target structural patterns for clustering is written as natural language prompts. These prompts enable the LLM to interpret the netlist as a graph and identify the target structural patterns. The identified clusters are treated as single placement instances to achieve structure-aware placement. The proposed approach allows flexible detection of target structures and remains robust to structural variations without explicit rule-based programming.
Experimental results on a DRAM peripheral circuit demonstrate a 80.6% reduction in the number of DRVs. Setup WNS improves by 0.9% while hold WNS degrades by 128%, highlighting the importance of timing-aware clustering as future work.
Event Type
Engineering Poster Gladiator
TimeWednesday, July 292:00pm - 2:11pm PDT
LocationDAC Pavilion, Exhibit Floor
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