Presentation
A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
DescriptionAdvanced‑node libraries must meet aggressive PPA targets across wide voltage ranges, including near‑/ultra‑low‑voltage operation where process variation is amplified and non‑Gaussian. Traditional sensitivity‑based LVF (SBA) fails to retain accuracy under these conditions, while Monte‑Carlo (MC) is impractical for full‑library, multi‑PVT production. We present a unified methodology that integrates
(i) ML‑based LVF to capture moments and sigma at ULV with production‑viable runtime,
(ii) MIS‑aware characterization to model simultaneous input switching for accurate gate delays—particularly on hold‑critical paths, and
(iii) in‑flow EM reliability generation and validation.
Across combinational and sequential cells, our ML‑LVF correlates closely with MC (comparable accuracy at a fraction of runtime), and MIS modeling closes the GLS vs. standalone delay gap observed on short paths. The flow also delivers signoff‑quality Liberty views with PrimeTime‑consistent timing/power correlation and enables early reliability checks. Overall, the methodology accelerates library turnaround while improving accuracy and reducing downstream timing/reliability closure risk for advanced‑node designs.
(i) ML‑based LVF to capture moments and sigma at ULV with production‑viable runtime,
(ii) MIS‑aware characterization to model simultaneous input switching for accurate gate delays—particularly on hold‑critical paths, and
(iii) in‑flow EM reliability generation and validation.
Across combinational and sequential cells, our ML‑LVF correlates closely with MC (comparable accuracy at a fraction of runtime), and MIS modeling closes the GLS vs. standalone delay gap observed on short paths. The flow also delivers signoff‑quality Liberty views with PrimeTime‑consistent timing/power correlation and enables early reliability checks. Overall, the methodology accelerates library turnaround while improving accuracy and reducing downstream timing/reliability closure risk for advanced‑node designs.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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