Presentation
Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
DescriptionThis study focuses on electromagnetic fault injection attacks.
The custom methods have been demanded such that consistently analyse both the electromagnetic irradiation and the resulting physical phenomena within the circuit.
Therefore, this research has developed an integrated analysis method combining an electromagnetic field solver and chip PDN modelling techniques.
The electromagnetic field solver models the EM coil and the metal forming the main power delivery network (PDN) within the chip in order to analyse induced currents.
The chip PDN model is an equivalent circuit model based on RLC networks created from design information.
This method was applied and analysed using a test chip.
The results showed that the heatmap changed depending on the position of the EM coil and the differences in the power delivery paths to the PDN.
Regarding the differences in power delivery paths, the voltage drop inside the chip during the attack was measured using on-chip voltage monitoring circuit, confirming agreement between simulation and measurements.
As this model can include logic transition information, it is expected that it can be extended to digital circuit fault analysis.
The custom methods have been demanded such that consistently analyse both the electromagnetic irradiation and the resulting physical phenomena within the circuit.
Therefore, this research has developed an integrated analysis method combining an electromagnetic field solver and chip PDN modelling techniques.
The electromagnetic field solver models the EM coil and the metal forming the main power delivery network (PDN) within the chip in order to analyse induced currents.
The chip PDN model is an equivalent circuit model based on RLC networks created from design information.
This method was applied and analysed using a test chip.
The results showed that the heatmap changed depending on the position of the EM coil and the differences in the power delivery paths to the PDN.
Regarding the differences in power delivery paths, the voltage drop inside the chip during the attack was measured using on-chip voltage monitoring circuit, confirming agreement between simulation and measurements.
As this model can include logic transition information, it is expected that it can be extended to digital circuit fault analysis.
Event Type
Engineering Poster Gladiator
TimeTuesday, July 285:51pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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