Presentation
3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Description3DIC chiplet heterogeneous integration faces significant challenges in cross-die timing signoff due to the lack of unified 3D PDKs and the inability of conventional STA to account for jitter from TSV+HB arrays. This paper proposes a 3DEM-driven PDK-independent STA approach for reliable cross-die timing signoff. The approach constructs cross-die channels with die final-stage buffers and cross-die sections, integrating 3D EM modeling for S-parameter acquisition, SPICE simulation for total jitter analysis, R/C parameter back-annotation, and jitter incorporation as uncertainty into STA. A case study on 9-layer stacking (1GHz) shows that the proposed method enables transmission pattern optimization (reducing jitter from 230.74ps to 120.28ps and achieving timing closure), which is unattainable with conventional STA. This work facilitates reliable and flexible 3DIC chiplet heterogeneous integration.
Event Type
Engineering Poster Gladiator
TimeTuesday, July 285:17pm - 5:25pm PDT
LocationDAC Pavilion, Exhibit Floor
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