Presentation
AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
DescriptionAs semiconductor designs scale to billions of transistors, compute demands for electronic design automation (EDA) increasingly exceed the capacity of traditional on-premises infrastructure. Migrating workloads to hybrid or cloud environments offers scalability, but many organizations face inefficiencies in job provisioning, resource utilization, and scheduling accuracy. This work introduces AI Assist for EDA Cloud Optimization, a framework leveraging graph neural networks (GNNs) and reinforcement learning (RL) to forecast compute requirements and optimize workload execution across heterogeneous environments.
By analyzing job metadata from synthesis, placement, and verification stages, AI Assist predicts runtime and resource needs prior to submission—reducing overprovisioning by 60–80% and improving runtime completion speed by 20–40% in test deployments. The adaptive scheduling layer learns policies that balance cost, performance, and licensing constraints across hybrid compute environments.
Complementary modules—such as placement optimization and hotspot prediction—apply similar AI paradigms to design optimization and verification, demonstrating measurable improvements in PPA efficiency and iteration time. Together, these solutions illustrate how AI Assist enables semiconductor firms to modernize their EDA workflows securely and efficiently while accelerating design convergence in the transition to cloud-scale engineering.
By analyzing job metadata from synthesis, placement, and verification stages, AI Assist predicts runtime and resource needs prior to submission—reducing overprovisioning by 60–80% and improving runtime completion speed by 20–40% in test deployments. The adaptive scheduling layer learns policies that balance cost, performance, and licensing constraints across hybrid compute environments.
Complementary modules—such as placement optimization and hotspot prediction—apply similar AI paradigms to design optimization and verification, demonstrating measurable improvements in PPA efficiency and iteration time. Together, these solutions illustrate how AI Assist enables semiconductor firms to modernize their EDA workflows securely and efficiently while accelerating design convergence in the transition to cloud-scale engineering.
Event Type
Engineering Presentation
TimeTuesday, July 2811:45am - 12:00pm PDT
LocationSeaside Ballroom A
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