Presentation
Maximize RoI Through Glitch Power Optimization at Early Design Stage
DescriptionAt advanced process nodes such as 5nm and 3nm, power efficiency is increasingly limited by glitch activity rather than functional switching alone. Aggressive timing closure, deep logic cones, and high fanout amplify delay mismatches, causing glitch power to contribute 15-25% of dynamic power in real silicon paths. When identified late in the flow, glitch-related inefficiencies are costly to fix and yield limited benefit. This work shows that early RTL-stage glitch optimization delivers significantly higher return on investment (ROI).
We present an RTL-level glitch analysis and optimization workflow using RTL Power Delay-Aware Glitch (DAG) Analysis, enabling designers to detect and address glitch behavior prior to synthesis. The methodology starts with top-level average power analysis, followed by hierarchical glitch reporting to localize glitch-prone logic. The Glitch Source Report ranks the top glitch-generating logic based on downstream impact, separating self-induced and propagated glitch power to guide prioritization.
The Detailed Glitch Report traces complete glitch propagation paths to terminating registers, revealing how logic depth, fanout, glitch event rates, and downstream capacitance amplify power loss. Across multiple advanced-node designs, targeted RTL fixes achieved 10-30% dynamic power reduction, demonstrating that early, delay-aware glitch optimization is a practical, high-ROI strategy for modern SoCs.
We present an RTL-level glitch analysis and optimization workflow using RTL Power Delay-Aware Glitch (DAG) Analysis, enabling designers to detect and address glitch behavior prior to synthesis. The methodology starts with top-level average power analysis, followed by hierarchical glitch reporting to localize glitch-prone logic. The Glitch Source Report ranks the top glitch-generating logic based on downstream impact, separating self-induced and propagated glitch power to guide prioritization.
The Detailed Glitch Report traces complete glitch propagation paths to terminating registers, revealing how logic depth, fanout, glitch event rates, and downstream capacitance amplify power loss. Across multiple advanced-node designs, targeted RTL fixes achieved 10-30% dynamic power reduction, demonstrating that early, delay-aware glitch optimization is a practical, high-ROI strategy for modern SoCs.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor