Presentation
A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
DescriptionUltra‑large digital designs at advanced technology nodes now include billions of instances, deep hierarchies, and highly complex clocking and interconnect structures, making traditional flat static timing analysis (STA) increasingly impractical. Timing closure cycles have become prohibitively long due to excessive runtime, memory demands, and limited visibility across block boundaries. This work presents a scalable and silicon‑correlated timing analysis and closure methodology tailored for these massive designs. The approach unifies Boundary Model, Context‑Aware Timing, and Advanced Multi‑Input Switching (AMIS) to deliver accurate hierarchical timing without requiring design flattening. Boundary Model preserves interface logic by abstracting internal logic in order to reduce design size, while Context‑Aware Timing ensures that each block's interface timing remains aligned with top‑level requirements, regardless of differences introduced by independently developed constraints. AMIS effectively addresses inherent optimism in single‑input switching by capturing simultaneous switching effects. Combined with Tempus ECO and Certus, the methodology enables fast, localized optimization and predictable convergence. Applied to a multi‑billion‑instance design across 150+ timing views, the flow demonstrates 3.5×–5× runtime improvement, 50–65% memory reduction, and strong correlation with flat STA. This scalable methodology provides a robust foundation for achieving efficient timing closure in emerging high‑performance systems.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor