Presentation
Methodology to Optimize the Length of Software Test Library (STL) to Reduce Execution-Time to Meet Both System and ISO-26262 ASIL-B Requirements
DescriptionSTL (Software Test Library) is a very common, if not the most common, Safety Mechanism (SM) used for ASIL-B designs, mostly for CPUs, DSPs, and the like. STL runs on the CPU in operational mode. The operational software is stopped to allow the STL to run.
Hence, if the STL run-time is long, it will reduce CPU availability and the overall system performance. Because of this, it is critical to reduce the execution time of the STL to lower its impact on the system performance
From the opposite side, to increase the Diagnostic Coverage (DC) to meet the ASIL-B requirements, STL often needs to be long, as more and more sections are added to cover undetectable faults.
In this presentation, we present a novel methodology, technology, and results from an actual project, where the team was able to reduce the STL total run time to below 3% of what it originally was at the beginning of the project, while keeping the same DC results.
Hence, if the STL run-time is long, it will reduce CPU availability and the overall system performance. Because of this, it is critical to reduce the execution time of the STL to lower its impact on the system performance
From the opposite side, to increase the Diagnostic Coverage (DC) to meet the ASIL-B requirements, STL often needs to be long, as more and more sections are added to cover undetectable faults.
In this presentation, we present a novel methodology, technology, and results from an actual project, where the team was able to reduce the STL total run time to below 3% of what it originally was at the beginning of the project, while keeping the same DC results.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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