Presentation
Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
DescriptionElectromigration and IR drop (EMIR) signoff at advanced process nodes demands prohibitively large compute resources, often requiring thousands of cores and multi day runtimes for full chip flat analysis. As design sizes and scenario counts increase, traditional methodologies fail to scale, limiting coverage and delaying signoff closure. This work presents a scalable Reduced Order Modeling (ROM)–based hierarchical EMIR signoff flow that delivers flat analysis level accuracy with dramatic improvements in turnaround time and memory efficiency.
The proposed flow abstracts each block into a scenario aware ROM containing geometry, circuit representation, demand currents, and decap models. These ROMs are generated once at block level and reused across all top level instantiations, enabling flexible configuration of detail granularity per instance. In full chip analysis, ROM consumption significantly reduces simulation complexity while preserving IR drop fidelity.
Results on a production scale GPU design demonstrate 86% runtime reduction (30.4 hrs → 4.21 hrs) and 52% lower memory usage, using identical core counts. IR drop correlation remains exceptionally strong: 99.9% of instances within ±10 mV, with peak delta under 15 mV across vectorless and DFT vector scenarios. These results establish ROM based EMIR analysis as a practical, high accuracy alternative to flat signoff, enabling broader scenario coverage, faster iteration, and scalable deployment across SoC design teams.
The proposed flow abstracts each block into a scenario aware ROM containing geometry, circuit representation, demand currents, and decap models. These ROMs are generated once at block level and reused across all top level instantiations, enabling flexible configuration of detail granularity per instance. In full chip analysis, ROM consumption significantly reduces simulation complexity while preserving IR drop fidelity.
Results on a production scale GPU design demonstrate 86% runtime reduction (30.4 hrs → 4.21 hrs) and 52% lower memory usage, using identical core counts. IR drop correlation remains exceptionally strong: 99.9% of instances within ±10 mV, with peak delta under 15 mV across vectorless and DFT vector scenarios. These results establish ROM based EMIR analysis as a practical, high accuracy alternative to flat signoff, enabling broader scenario coverage, faster iteration, and scalable deployment across SoC design teams.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor