Presentation
Beyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI Accelerators
DescriptionModern AI accelerators, such as Meta's MTIA, rely on massive arrays of Processing Elements (PEs) to maximize compute density. This architecture creates a design structure known as MIMs (Multiple Instantiated Modules). While these repetitive structures are essential for physical design optimization, they create a verification nightmare when doing flat analysis. Most modern flows rely on hierarchical verification using abstract models of smaller blocks at top level. However, in massive AI chips even this approach falls short due to the sheer volume of redundant Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) checks generated when large subsystems are instantiated repeatedly, causing chip-level flow runtimes to become unmanageable.
This paper presents a static verification methodology designed to overcome these scalability challenges in reticle-limit AI chips. While standard hierarchical flows utilizing Block Abstract Models attempt to manage complexity, the physical repetition of MIMs results in top analysis runs exceeds 26 hours and consuming up to 12x more memory due to redundant reporting.
To address this, we propose an RTL-based "stubbing" technique that selectively isolates unique instances of large blocks, such as Processing Elements, while neutralizing redundant copies via parameterized RTL defines. By shifting signoff to the block level and reducing the scope of top-level analysis, this methodology reduces the number of flat instances from 14.4 billion to 1.1 billion. Consequently, this approach eliminates redundant crossings, slashing verification runtime by 90% (down to 3.5 hours) and significantly reducing storage requirements, thereby enabling faster design convergence and feedback loops
This paper presents a static verification methodology designed to overcome these scalability challenges in reticle-limit AI chips. While standard hierarchical flows utilizing Block Abstract Models attempt to manage complexity, the physical repetition of MIMs results in top analysis runs exceeds 26 hours and consuming up to 12x more memory due to redundant reporting.
To address this, we propose an RTL-based "stubbing" technique that selectively isolates unique instances of large blocks, such as Processing Elements, while neutralizing redundant copies via parameterized RTL defines. By shifting signoff to the block level and reducing the scope of top-level analysis, this methodology reduces the number of flat instances from 14.4 billion to 1.1 billion. Consequently, this approach eliminates redundant crossings, slashing verification runtime by 90% (down to 3.5 hours) and significantly reducing storage requirements, thereby enabling faster design convergence and feedback loops
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor