Presentation
Zero‑Glitch Confidence: An End‑to‑End Static, Formal & Simulation Methodology
DescriptionGlitches in synthesized netlists continue to pose significant risks to functional correctness, especially in deeply optimized, high‑performance digital designs. While structural glitch analysis provides fast, design‑wide coverage, it alone cannot fully capture the functional conditions under which hazards become observable. Conversely, formal verification and dynamic simulation each offer deeper semantic insight but suffer from scalability or stimulus limitations. This work presents a unified methodology that combines static/structural glitch detection with formal and simulation-based verification to deliver end‑to‑end confidence in glitch‑free implementations.
We introduce techniques for cross‑domain correlation, where structural analysis first identifies potential hazard sites, which are then refined through formal trace generation or targeted simulation. For example, in control-heavy FSM logic, structural + simulation verification enables exhaustive proof that identified glitch cones cannot propagate to state elements under any reachable condition. Similarly, in asynchronous FIFO, Formal techniques are used to identify glitches in Empty signal. Experimental results show that the combined flow significantly reduces false positives, improves coverage, and enables practical signoff for glitch vulnerabilities in complex SoC blocks.
We introduce techniques for cross‑domain correlation, where structural analysis first identifies potential hazard sites, which are then refined through formal trace generation or targeted simulation. For example, in control-heavy FSM logic, structural + simulation verification enables exhaustive proof that identified glitch cones cannot propagate to state elements under any reachable condition. Similarly, in asynchronous FIFO, Formal techniques are used to identify glitches in Empty signal. Experimental results show that the combined flow significantly reduces false positives, improves coverage, and enables practical signoff for glitch vulnerabilities in complex SoC blocks.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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