Presentation
Hierarchical Cost-Efficient IR Methodology for AI SoCs
DescriptionIR (voltage) drop signoff represents a critical bottleneck in modern SOC designs. In modern large-scale designs (e.g., GPUs, AI), traditional flat IR analysis has become computationally infeasible due to datacenter limitations. On the contrary, resorting to design fragmenting and running flat IR drop on multiple partitions parallelly is time-consuming and has the risk of compromised QoR due to missed boundary conditions, assumed symmetry and coordination overhead.
This paper proposes a hierarchical methodology to address capacity and performance in the context of multiple concurrent designs. First, an initial EMIR run is completed at the block level with adequate coverage. Second, a hierarchical model of the blocks, called the reduced order model (ROM), is then created with these block runs. The full chip IR (complete metal stack) is then run with these models. This methodology has multiple-fold performance improvement with its accuracy within a small margin of error compared to traditional flat analysis. This methodology hence fundamentally enables full-chip and 3DIC IR closure for AI SOCs that was previously impossible.
Keywords: Dynamic IR, hierarchical modelling, hierarchical signoff
This paper proposes a hierarchical methodology to address capacity and performance in the context of multiple concurrent designs. First, an initial EMIR run is completed at the block level with adequate coverage. Second, a hierarchical model of the blocks, called the reduced order model (ROM), is then created with these block runs. The full chip IR (complete metal stack) is then run with these models. This methodology has multiple-fold performance improvement with its accuracy within a small margin of error compared to traditional flat analysis. This methodology hence fundamentally enables full-chip and 3DIC IR closure for AI SOCs that was previously impossible.
Keywords: Dynamic IR, hierarchical modelling, hierarchical signoff
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor