Presentation
Flexible NoC IP: Software Based Configuration and Fast Performance Validation
DescriptionModern on‑chip network (NoC) IP must support extensive configurability to meet the needs of increasingly diverse systems. This flexibility spans high‑level parameters as well as fine‑grain control over topology, channel assignments, virtual channels, link widths, router microarchitecture, and routing policies. While powerful, this level of configurability increases the complexity of IP setup, architectural decision‑making, and system‑level validation.
We present a software‑defined methodology for configuring and validating highly flexible NoC IP. Using Baya Systems' Fabric Studio as an example, we illustrate how a software‑based input model captures design intent and system constraints, enabling automated generation of NoC implementations with complete topology control while ensuring correctness and deadlock avoidance across standalone and multi‑chiplet systems.
A key part of the methodology is a fast C++‑based simulation engine that models traffic flows, bandwidth demands, latency targets, and quality‑of‑service objectives. This allows rapid evaluation of NoC architectures prior to RTL development and supports extensive design‑space exploration that would be impractical using RTL‑centric flows.
By shifting configuration complexity and early performance validation into software, this approach improves scalability, reduces integration risk, and enables engineering teams to deliver highly configurable NoC IP with greater confidence. The presentation summarizes lessons learned in developing and deploying this methodology for industrial NoC design.
We present a software‑defined methodology for configuring and validating highly flexible NoC IP. Using Baya Systems' Fabric Studio as an example, we illustrate how a software‑based input model captures design intent and system constraints, enabling automated generation of NoC implementations with complete topology control while ensuring correctness and deadlock avoidance across standalone and multi‑chiplet systems.
A key part of the methodology is a fast C++‑based simulation engine that models traffic flows, bandwidth demands, latency targets, and quality‑of‑service objectives. This allows rapid evaluation of NoC architectures prior to RTL development and supports extensive design‑space exploration that would be impractical using RTL‑centric flows.
By shifting configuration complexity and early performance validation into software, this approach improves scalability, reduces integration risk, and enables engineering teams to deliver highly configurable NoC IP with greater confidence. The presentation summarizes lessons learned in developing and deploying this methodology for industrial NoC design.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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