Presentation
FPGA-to-ASIC Conversion via Hierarchical Wrapping
DescriptionModern FPGA designs are highly parameterized, hierarchical, and optimized for top-down methodologies, while ASIC designs demand bottom-up flows that emphasize physical layout and timing closure. Bridging these paradigms is nontrivial due to differences in hierarchy handling, parameter resolution, and constant signal treatment. We present Morph-Localize, an automated methodology integrated into EDA toolchains that converts FPGA designs into ASIC-ready implementations. The approach introduces hierarchical boundary wrapping to preserve design hierarchy while enabling physical partitioning, parameter resolution and uniquification to eliminate runtime variability, and constant propagation with port pruning to reduce routing congestion and improve synthesis efficiency. A top-down equivalence check ensures functional correctness. Applied within IBM's Nexus chip flow, Morph-Localize demonstrates significant improvements in synthesis runtime, area utilization, and timing closure, reducing manual intervention and accelerating time-to-market for complex ASIC projects.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor