Presentation
ENHANCED AUTOMATION FOR GENERATING LOGIC-OPTIMIZATION ECOs (EAGLE) IN SIGNOFF
DescriptionModern high-performance digital circuits face significant challenges in achieving optimal timing closure due to the complexity of designs with millions of transistors. While APR tools provide sophisticated optimization capabilities, they often compromise on local optimizations due to global constraints, tool limitations, and PPA trade-offs. Non-optimized structures residing on critical paths directly impact on the achievable operating frequency, creating performance bottlenecks. During the ECO phase, setup violating paths undergo re-ordering, creating opportunities for logic optimization. The positive slack paths, which were not optimization targets during synthesis, become exposed during ECOs and offer greater potential for logic optimization to achieve timing targets. However, current solutions suffer from lack of Primetime compatibility and absence of direct APR tool integration, necessitating manual intervention that extends design closure timelines. EAGLE overcomes these constraints through a comprehensive Primetime-integrated framework that leverages ECO-phase optimization opportunities and delivers APR tool-compatible ECOs directly.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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