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Automatic SDC Creation for Static Timing Analysis
DescriptionTiming constraints are written to specify the design intent. SDC constraints are needed to properly: specify clocks in a design, instantiate on the correct pins/ports, compute uncertainty for clocks, and assert behavior/interaction of clocks in a design.

Timing constraints are typically manually written by the designer. The work can be tedious, time-consuming, prone to missing an interaction, or prone to calculation errors – leading to lengthy iterations, and the risk of hardware fails or excessive power.

We present a novel tool, ClockACE, to automatically create and apply all necessary timing constraints.
This saves significant amount of work for the designer. This prevents human error in computation or missing constraints. Any change to a clock spec is automatically re-computed within the timing run.
In this paper we present ClockACE for automatic constraint generation. We highlight a specific example using generated clocks, and the challenges with implementation of this clocking paradigm. We show how ClockACE handles this scenario automatically.