Presentation
INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
DescriptionConventional Reset Domain Crossing (RDC) practices rely on pessimistic structural analysis, often ignoring critical design intent. This oversight causes two major issues: millions of false metastable paths are reported due to ignored hierarchical reset sequencing, and tools fail to recognize reset-driven clock-gaters that physically prevent metastability. Consequently, designers are burdened by a manual, trial-and-error process of defining ignore-paths and constraints to silence this noise.
This paper presents an intelligent RDC methodology that utilizes boolean reasoning to automatically extract design intent from the hardware. The proposed flow introduces native reset sequencing awareness to learn assertion ordering and reset-driven clock-off awareness to determine when reset assertions disable capture clocks. By automatically filtering functionally impossible paths, the methodology provides accurate reporting with dramatically reduced noise.
The outcome is a practical, adoption-ready RDC solution that eliminates the burden of manual false-path definitions and constraint tuning. This approach ensures that RDC analysis is aligned with actual silicon behavior rather than testing a designer's ability to manually write complex constraints. Overall, the flow improves verification quality while significantly reducing the manual effort required for RDC closure.
This paper presents an intelligent RDC methodology that utilizes boolean reasoning to automatically extract design intent from the hardware. The proposed flow introduces native reset sequencing awareness to learn assertion ordering and reset-driven clock-off awareness to determine when reset assertions disable capture clocks. By automatically filtering functionally impossible paths, the methodology provides accurate reporting with dramatically reduced noise.
The outcome is a practical, adoption-ready RDC solution that eliminates the burden of manual false-path definitions and constraint tuning. This approach ensures that RDC analysis is aligned with actual silicon behavior rather than testing a designer's ability to manually write complex constraints. Overall, the flow improves verification quality while significantly reducing the manual effort required for RDC closure.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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