Presentation
Bridging the Modeling Gap: State-Aware Liberty Enhancements for Multimode IP Designs
DescriptionModern SoCs integrate a wide range of IP types: I/O's, SerDes, PLLs, DACs, ADCs, memories...each operating across multiple protocols, voltage domains, and performance modes. While characterization flows accurately capture this mode dependent electrical behavior (including distinct thresholds, load limits, slew limits, and rail sensitivities), the Liberty (.lib) format remains largely scalar and static.
Key attributes such as max_capacitance, max_transition, and voltage_map can only be expressed as fixed per pin values, and existing constructs like when or mode_support affect only logical activation, not the underlying electrical state of the IP.
This fundamental limitation forces designers to maintain multiple mode specific .lib files, which increases configuration overhead and risks silent extrapolation during sign off when tools operate outside valid characterized ranges.
We propose a State Aware Liberty Modeling approach that introduces explicit constructs for both electrical configuration states and operational modes (protocol specific electrical constraints). This allows voltage mapping, thresholds, load limits, and slew limits to vary per mode within a single unified library. These enhancements generalize across all IP types, improving silicon to model correlation and enabling robust, mode accurate timing and power sign off for next generation SoC architectures.
Key attributes such as max_capacitance, max_transition, and voltage_map can only be expressed as fixed per pin values, and existing constructs like when or mode_support affect only logical activation, not the underlying electrical state of the IP.
This fundamental limitation forces designers to maintain multiple mode specific .lib files, which increases configuration overhead and risks silent extrapolation during sign off when tools operate outside valid characterized ranges.
We propose a State Aware Liberty Modeling approach that introduces explicit constructs for both electrical configuration states and operational modes (protocol specific electrical constraints). This allows voltage mapping, thresholds, load limits, and slew limits to vary per mode within a single unified library. These enhancements generalize across all IP types, improving silicon to model correlation and enabling robust, mode accurate timing and power sign off for next generation SoC architectures.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor