Presentation
Achieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification
DescriptionAutomotive Ethernet ICs require robust design and extensive high-sigma verification to meet stringent "zero defect" quality standards, with every device parameter required to yield at least 5σ. Robustness by design is time-consuming and introduces PPA and EMI tradeoffs that must be mitigated by parameter optimization. Traditional brute-force Monte Carlo simulations are impractical for high-sigma verification, and manually trimming and optimizing parameters is time-intensive.
This paper presents an innovative AI-powered methodology that significantly accelerates high-sigma verification, trimming, and optimization for automotive ethernet solutions. This approach integrates adaptive AI for efficient parameter robustness screening and ML-based sensitivity analysis for identifying parameters that most contribute to variation, while intelligent, built-in trimming and optimization in-the-loop automatically mitigate sensitive parameters to bring critical measurements back into spec.
In the example Bandgap Reference to Low-Dropout (LDO) circuit, the proposed methodology achieves strong correlation with silicon production data, while providing >64,000x speedup over brute-force methods. This solution accurately predicts high-sigma failures, automatically determines trim codes, and automatically optimizes targets with minimal simulations, leading to substantial speedups, reduced resource requirements, and faster time-to-market.
This paper presents an innovative AI-powered methodology that significantly accelerates high-sigma verification, trimming, and optimization for automotive ethernet solutions. This approach integrates adaptive AI for efficient parameter robustness screening and ML-based sensitivity analysis for identifying parameters that most contribute to variation, while intelligent, built-in trimming and optimization in-the-loop automatically mitigate sensitive parameters to bring critical measurements back into spec.
In the example Bandgap Reference to Low-Dropout (LDO) circuit, the proposed methodology achieves strong correlation with silicon production data, while providing >64,000x speedup over brute-force methods. This solution accurately predicts high-sigma failures, automatically determines trim codes, and automatically optimizes targets with minimal simulations, leading to substantial speedups, reduced resource requirements, and faster time-to-market.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor