Presentation
AI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level Shifters
DescriptionLevel shifters are critical for reliable cross-voltage domain communication: their failure risks the integrity of the circuit, excessive power dissipation, and damage to components. Extensive verification is required to mitigate their susceptibility to device variability and multiple failure mechanisms. Traditional brute-force Monte Carlo analysis is infeasible for evaluating all failure modes across large corner sets at advanced nodes, making accurate, timely verification challenging.
This paper introduces an AI-powered, high-throughput batch flow for fast, accurate signoff verification of single and multibit level shifter cells. Adaptive AI performs rapid identification of worst-case corners, which are then verified with AI-powered, brute-force accurate high-sigma technology. This precision deployment optimizes runtime and resources by running high-sigma verification only when necessary.
The proposed methodology demonstrates significant improvements over previous methods. 3σ single-cell validation was 3x faster than traditional brute-force Monte Carlo, and high-sigma verification precision deployment reduced overall runtime by 10x across 256 cells at 6σ. Targeted analysis validated glitch heights in multibit level shifters at 3σ and 6σ, with precision deployment reducing overall runtime by >14x. This AI-driven solution optimizes compute and engineering resources to provide timely, accurate guidance on reduced verification timelines, ensuring full-coverage functional robustness, improved silicon quality, and faster time-to-market.
This paper introduces an AI-powered, high-throughput batch flow for fast, accurate signoff verification of single and multibit level shifter cells. Adaptive AI performs rapid identification of worst-case corners, which are then verified with AI-powered, brute-force accurate high-sigma technology. This precision deployment optimizes runtime and resources by running high-sigma verification only when necessary.
The proposed methodology demonstrates significant improvements over previous methods. 3σ single-cell validation was 3x faster than traditional brute-force Monte Carlo, and high-sigma verification precision deployment reduced overall runtime by 10x across 256 cells at 6σ. Targeted analysis validated glitch heights in multibit level shifters at 3σ and 6σ, with precision deployment reducing overall runtime by >14x. This AI-driven solution optimizes compute and engineering resources to provide timely, accurate guidance on reduced verification timelines, ensuring full-coverage functional robustness, improved silicon quality, and faster time-to-market.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor