Presentation
Dynamic CDC Verification Using SVA for Waiver Review
DescriptionAsynchronous clock domains in modern SoC designs present critical verification challenges, as Clock Domain Crossing (CDC) issues remain the second most common cause of silicon re-spins. While static CDC ensures structural synchronization, it relies on manual constraints and waivers that may be inaccurate or hide functional bugs. Furthermore, formal analysis often leaves properties "partially proven" due to computational complexity.
This paper proposes a closed-loop methodology to validate these "design intent" assumptions dynamically. The flow begins by running structural CDC and filtering results to identify waived paths. These waivers—including those translated from TCL to constraint formats—are converted into protocol-aware SystemVerilog Assertions (SVA). By integrating these SVAs into dynamic simulation, engineers can stress-test protocols like data-hold and glitch protection.
If simulations pass, waiver validity is confirmed for sign-off; failures trigger design or constraint refinement. This methodology is a "MUST" for SoC design, uncovering corner-case bugs unreachable via manual reviews. Key advantages include significantly reduced Turnaround Time (TAT) and high-quality sign-off guaranteed by measurable assertion coverage.
This paper proposes a closed-loop methodology to validate these "design intent" assumptions dynamically. The flow begins by running structural CDC and filtering results to identify waived paths. These waivers—including those translated from TCL to constraint formats—are converted into protocol-aware SystemVerilog Assertions (SVA). By integrating these SVAs into dynamic simulation, engineers can stress-test protocols like data-hold and glitch protection.
If simulations pass, waiver validity is confirmed for sign-off; failures trigger design or constraint refinement. This methodology is a "MUST" for SoC design, uncovering corner-case bugs unreachable via manual reviews. Key advantages include significantly reduced Turnaround Time (TAT) and high-quality sign-off guaranteed by measurable assertion coverage.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor