Presentation
Early DEF-Based Hierarchical Power Grid Shorts Analysis
DescriptionHierarchical power grid shorts represent a critical challenge in modern chip design, typically discovered late in the schedule during physical verification and LVS analysis at integration, causing significant delays and expensive fixes near tapeout. This work presents an innovative DEF-based methodology to detect power grid shorts early in the PNR flow with exact coordinate reporting. The approach analyzes power and ground net shapes to identify unintended collisions between different net types, particularly for multi-voltage domain crossings. By processing DEF data from individual PNR blocks in the context of their hierarchical placement, the methodology enables shorts identification in hours rather than days. This system integrated at the floorplan level of the PNR implementation flow significantly reduces physical verification churn, eliminates weeks of LVS iteration, and improves design schedule predictability while providing precise location information for rapid resolution.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor