Presentation
Timing Aware Power Integrity Enhancement in Performance Core Architectures Through Advanced Custom Global PG-Fill Techniques
DescriptionPower integrity in high-performance computing systems is crucial for ensuring reliable and efficient operation. With each generation, high-performance CPU cores are significantly increasing in area and power to meet compute needs. Power integrity has become a critical factor in CPU silicon performance, as CPUs are starting to throttle before achieving the STA frequency due to power budgets and thermal limitations. General-purpose CPUs used in various product segments often face coverage issues, making it challenging to sign off on power integrity with a limited number of vectors. Therefore, a global solution is needed to ensure robust electrical performance and reliability.
Global PG-Fill provides reinforcement to the existing Power Delivery Network (PDN), improving PDN resistance, reducing voltage drops, and minimizing electromagnetic interference.
In this paper, we discuss how we utilized opportunistic track-based PG-Fill using Cadence Pegasus and optimally integrated it with the existing PDN to enhance power integrity while addressing challenges such as runtime and timing degradation. We propose our custom solution by optimally controlling STAMP lengths, adding additional PG VIAs, and improving the overall effective resistance of the design. We also address key challenges, such as timing degradation caused by PG-Fill, and how our custom solution helped to minimize these issues.
Using the proposed custom solution, we achieved an improvement of approximately 20% in overall PDN resistance and 88% cleanup in overall dynamic IR violations, resulting in a more robust design. All of this was achieved without introducing any additional DRC violations.
Global PG-Fill provides reinforcement to the existing Power Delivery Network (PDN), improving PDN resistance, reducing voltage drops, and minimizing electromagnetic interference.
In this paper, we discuss how we utilized opportunistic track-based PG-Fill using Cadence Pegasus and optimally integrated it with the existing PDN to enhance power integrity while addressing challenges such as runtime and timing degradation. We propose our custom solution by optimally controlling STAMP lengths, adding additional PG VIAs, and improving the overall effective resistance of the design. We also address key challenges, such as timing degradation caused by PG-Fill, and how our custom solution helped to minimize these issues.
Using the proposed custom solution, we achieved an improvement of approximately 20% in overall PDN resistance and 88% cleanup in overall dynamic IR violations, resulting in a more robust design. All of this was achieved without introducing any additional DRC violations.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor