Presentation
Accelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level Emulation
DescriptionThis paper describes the development of a full-chip gate-level emulation environment that enables DFT verification and the successful application of Debug STIL vectors generated by the Tessent DFT tool in the Veloce emulation environment, significantly improving debuggability and shortening the product verification time.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor