Presentation
Next-Generation Power Grid Robustness: Automated Via Enhancement with Calibre
DescriptionSemiconductor design at advanced process nodes is facing major hurdles, particularly the increased risk of IR-drop and electromigration (EM) failures. These issues are largely due to higher current densities and thinner BEOL stacks. Furthermore, complex modern lithography and the late identification of design flaws complicate the creation of reliable power delivery networks (PDN), frequently resulting in lengthy ECO cycles and delayed schedules.
To combat these PDN issues, the Calibre Design Enhancer Via Flow was developed as an automated, signoff-quality solution. This tool utilizes a technology-agnostic strategy supporting DEF and OASIS formats, enabling seamless integration across different process nodes and design stages. By incorporating signoff-level rule awareness, it ensures that via placements are DRC-clean and correct-by-construction.
The flow improves vertical connectivity and mitigates EM hotspots by strategically placing redundant vias at missed locations and critical junctions. This reduces IR-drop and increases signoff confidence. This scalable methodology, designed for sub-3nm processes, enhances PDN durability and removes the need for manual iterations.
To combat these PDN issues, the Calibre Design Enhancer Via Flow was developed as an automated, signoff-quality solution. This tool utilizes a technology-agnostic strategy supporting DEF and OASIS formats, enabling seamless integration across different process nodes and design stages. By incorporating signoff-level rule awareness, it ensures that via placements are DRC-clean and correct-by-construction.
The flow improves vertical connectivity and mitigates EM hotspots by strategically placing redundant vias at missed locations and critical junctions. This reduces IR-drop and increases signoff confidence. This scalable methodology, designed for sub-3nm processes, enhances PDN durability and removes the need for manual iterations.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor